1. Field of the Invention
The present invention relates to an improvement of performance and reliability of a MOS type field effect transistor.
2. Description of the Background Art
Conventionally, the degree of integration of semiconductor devices have been improved by miniaturizing the structure of the devices by virtue of the development of fine processing technique. In a MOS type field effect transistor (Metal-Oxide-Semiconductor Field Effect Transistor; hereinafter referred to as a MOSFET), a gate length is shortened from the order of microns to the order of submicrons as the device structure has been miniaturized. As the gate length become shorter, the channel length also becomes shorter, causing a so called short channel effect. More specifically, as the channel length becomes shorter, the electric field concentrates near the drain, and therefore the generation of hot carriers has become a serious problem. The hot carriers enter the gate oxide film, causing changes of the threshold voltage on time basis degrading mutual conductance, thereby damaging the reliability of the MOSFET. A LDD (Lightly Doped Drain) structure is one example of a MOSFET structure proposed to solve the problem derived from the generation of hot carriers. FIG. 1 shows a cross sectional structure of an n channel LDD MOSFET, disclosed in "Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology"; P. J. TSANG et al, IEEE Trans. Electron Devices., ED-29., 590, 1982. Referring to FIG. 1, a gate oxide film 2 is formed on a surface of a p type silicon substrate 1. A gate electrode 3 formed of polysilicon is formed on a surface of the gate oxide film 2. Sidewall spacers 4 of insulating films are formed on both sides of the gate electrode 3. The surface of the silicon substrate 1 covered with the gate electrode 3 will be a channel region 5. Each of two n type impurity regions 6 and 7 formed on the surface of the silicon substrate 1 comprises two layer structure having different concentrations. The n.sup.+ type impurity regions 6a and 7a having higher impurity concentration respectively have n.sup.- type impurity regions 6b and 7b having lower impurity concentration on the side of the channel region 5. The n.sup.- type impurity regions 6b and 7b having lower concentration are formed directly below and covered with the sidewall spacers 4.
The principle of the LDD structure shown in FIG. 1 will be described with reference to FIG. 2. A source 7 and a substrate 1 of a MOSFET are grounded to a potential of 0 V, for example, and a drain 6 is connected to a supply voltage (5 V, for example). Consequently, a reverse bias is applied to a p/n junction between the n type drain portions 6a and 6b and the p type semiconductor substrate 1 to generate a high electric field. The electric field at the drain is released more and more as a width of a depletion layer is made wider and wider. Generally, the width of the depletion layer of the p/n junction is represented by the following equation ##EQU1## wherein N.sub.A represents an acceptor concentration, N.sub.D represents a doner concentration, .epsilon.s represents a permittivity of the semiconductor, q represents an amount of charge, and w represents the width of the depletion layer. When the n type impurity concentration is very much higher than the impurity concentration of the p type semiconductor, that is, N.sub.D &gt;&gt;N.sub.A, the width of the depletion layer will be ##EQU2## When the n type impurity concentration is low and equal to the concentration of the p type semiconductor substrate, that is, N.sub.A =N.sub.D, the width of the depletion layer will be ##EQU3## Therefore, the electric field concentration is much more released at the p/n junction of the n.sup.- /p.sup.- substrate having lower concentration. Accordingly, the LDD MOSFET provides n.sup.- type impurity regions 6b and 7b having lower concentration at the p/n junction between the substrate 1 and the n.sup.+ type impurity regions 6a and 7a having higher concentration in order to release the electric field. Further, the generation of hot carriers is suppressed by releasing the electric field.
However, the LDD MOSFET newly provides two problems.
The first problem is decrease of on-resistance of the MOSFET, caused by the newly provided n.sup.- type impurity region having lower concentration serving as a parasitic resistance. This will be described with reference to FIGS. 2 and 3.
The operation of the MOSFET can be divided into two, namely, the operation in a pentode region (FIG. 2) in which the drain voltage V.sub.D is larger than the gate voltage V.sub.G (V.sub.D &gt;V.sub.G) and an operation in a triode region (FIG. 3) in which the gate volta V.sub.G is much larger than the drain voltage (V.sub.G &gt;&gt;V.sub.D). In the pentode region shown in FIG. 2, a depletion region having high resistance is formed between an inverted layer 8 and drains 6a and 6b formed of n.sup.- /n.sup.+. In addition to the channel resistance of the inverted layer 8, the resistance of the n.sup.- type impurity region 7b having the lower concentration at the source side, the resistance of the drain side depletion layer 9 and the resistance of the n type impurity region 6b on the side of the drain serving as parasitic resistances cause the decrease of the drain current. In the triode region, the resistance of the n.sup.- type impurity region 7b on the source side and the resistance of the drain side n.sup.- type impurity region 6b as parasitic resistances lower the on-resistance of the MOSFET as shown in FIG. 3.
The second problem relates to the hot carriers. In the drain structure of a conventional LDD MOSFET, hot carriers having larger energy than in the thermal equilibrium state are generated on the surface of the n.sup.- type impurity region 6b having lower concentration, and the generated hot carriers are implanted into the sidewall spacers 4 of the gate electrode 3. Consequently, the surface of the n.sup.- type impurity region 6b on the drain side is depleted, raising the resistance of the region, thereby degrading the drain characteristics of the MOSFET.
In order to solve these problems, the LDD structure has been improved. In the improvement, the n.sup.- type impurity region having lower concentration is arranged directly below the gate electrode, which is called a gate overlapped LDD structure. This is disclosed in "A NOVEL SUBMICRON LDD TRANSISTOR WITH INVERSE-T GATE STRUCTURE"; T. Y. HUANG et al. Technical Digest of International Electron Devices Meeting, 1986 p. 742, and "THE IMPACT OF GATE-DRAIN OVERLAPPED LDD (GOLD) FOR DEEP SUBMICRON VLSI'S"; R. IZAWA et al., Technical Digest of International Electron Devices Meeting, 1987, p. 38. In the following, a MOSFET having the gate overlapped LDD structure will be described with reference to the first mentioned article. FIGS. 4A to 4F show steps of manufacturing the gate overlapped LDD.
First, a gate oxide film 11, a polysilicon layer 12 and a silicon oxide film 13 are formed in this order on a silicon substrate 10. A resist 14 is applied and patterned into a prescribed pattern (FIG. 4A).
Thereafter, the silicon oxide film 13 is etched using the resist 14 as a mask, and the polysilicon layer 12 is removed to some extent by etching. The thickness of the remaining polysilicon layer 12b is 50 to 100 nm (FIG. 4B). Thereafter, phosphorus ions are implanted to a low concentration in the surface of the silicon substrate using the patterned silicon oxide film 13 and the polysilicon layer 12 therebelow as masks, to form an n.sup.- type impurity region 15 (FIG. 4C).
Thereafter, a silicon oxide film is deposited on the surfaces of the first silicon layer 12 and the like. This is anisotropically etched to form a sidewall spacer 17 (FIG. 4D).
Thereafter, the polysilicon layer 12b is etched using the sidewall spacer 17 as a mask to form a gate electrode 18 having an inverted T shape (FIG. 4E).
Finally, arsenic (As) is ion implanted using the sidewall spacer 17 and the like as masks to form an n.sup.+ type impurity region 19. Thermal oxidation is carried to activate the impurity ions (FIG. 4F).
Through the above described steps, a MOSFET having a gate overlapped LDD structure is manufactured in which the gate electrode 18 has an inverted T shape and the n.sup.- type impurity region 15 is fully covered with the gate electrode 18. The gate overlapped LDD structure can prevent depletion of the surface of the n.sup.- type impurity region, since the n.sup.- type impurity region is under the electric field from the gate electrode. The function and effect of this structure will be described later.
However, in the conventional gate overlapped LDD structure, the gate electrode has a cross section with uneven gate length such as the inverted T shape, due to the limitation in manufacturing. Therefore, compared with a conventional gate electrode having a rectangular cross section, the effective conductive area is reduced, increasing the wiring resistance of the gate electrode.
As for the manufacturing method, the gate electrode of the inverted T shape is formed by stopping the etching at the intermediate portion of the polysilicon layer. However, the control of the etching amount of the polysilicon layer is difficult, whereby the amount of etching becomes uneven on the wafer, decreasing the production yield.
In a gate overlapped LDD MOSFET shown in the latter mentioned article, the gate electrode also has a cross section with an uneven gate length, and the manufacturing method thereof requires complicated process steps including patterning of a layer serving as a mask for ion implantation.